As is known, inductors generate magnetic fields. Conventional embedded (“on-chip”) spiral inductors, such as found in high-speed and RF applications, are sometimes fabricated using a backend of the line (“BEOL”) process which is compatible with the formation of metal layers.
On-chip inductors are conventionally made of a single metal layer in a planar spiral pattern. The resultant magnetic flux from such on-chip inductors is in a direction that couples with a silicon substrate. The magnetic coupling of the magnetic flux generated by an inductor with such substrate promotes eddy currents, which may lead to a low gain (“Q-factor”) at high frequencies. To enhance inductor gain, others have proposed having: a higher substrate resistance, such as by use of an epitaxial layer; laminated conductive patterns, such as polysilicon strips; or a larger inductor to substrate distance, such as forming an inductor at a final metal layer in order to reduce eddy current. Unfortunately, these various techniques may add cost and/or may not provide a sufficient reduction in magnetic coupling between magnetic flux generated by an inductor and a substrate.
The inductance of a spiral inductor is roughly proportional to N2A, where N is the number of turns of such spiral inductor, and A is the cross-sectional area of wires forming turns of such spiral inductor. Conventional on-chip inductors use a significant amount of area and sometimes use dedicated metal layers to reach target inductances and Q-factor values. Metal thickness, width, and spacing between turns may be large to reduce series resistance and shunt capacitance in order to obtain more substantial gain. Furthermore, to avoid adverse effects associated with a magnetic field which is orthogonal to the upper surface plane of a substrate as generated by a planar spiral inductor, design rules conventionally forbid placement of any devices, such as transistors, directly underneath or in near proximity to an inductor, as such magnetic field may have negative impact on behavior of such devices. This placement restriction of an on-chip inductor may thus cost a significant amount of semiconductor area.
Accordingly, it would be desirable and useful to provide means that avoids one or more of the above mentioned limitations of on-chip planar spiral inductors.